Quick starter guide for those who are interested in open source ASIC development. Tiny Tapeout is an open source ASIC (chip) tool chain for students and hobbyists. Commercial EDA tools and licenses are costly so it’s great that chip design is becoming more affordable and accessible.

LibreLane + Nix + SPM Flow (Step-by-Step)

Step 1 - Install curl

sudo apt-get install -y curl

Step 2 - Install Nix

Nix is basically a way to make software environments fully controlled, repeatable, and isolated. In this case (LibreLane + ASIC tools), it ensures the entire toolchain behaves the same every time we run it.

curl --proto '=https' --tlsv1.2 -fsSL https://artifacts.nixos.org/nix-installer | sh -s -- install --no-confirm --extra-conf "
    extra-substituters = https://nix-cache.fossi-foundation.org
    extra-trusted-public-keys = nix-cache.fossi-foundation.org:3+K59iFwXqKsL7BNu6Guy0v+uTlwsxYQxjspXzqLYQs=
    extra-experimental-features = nix-command flakes
"

After installation:

    Restart your terminal
    Enter your password if prompted
    First run may take several minutes

Step 3 - Clone LibreLane

git clone https://github.com/librelane/librelane
cd librelane

If already cloned:

cd librelane

Step 4 - Enter Nix shell

nix-shell

First time startup may take several minutes due to package downloads.

Step 5 - Check example designs

ls librelane/examples/

You should see:

    spm
    hold_eco_demo
    spm-user_project_wrapper

For beginners, use:

spm

What does a SPM do?

A Serial-Parallel Multiplier multiplies two numbers together:

x[31:0] - the full 32-bit parallel input (loaded all at once)
a[31:0] - fed in 1 bit per clock cycle, serially (LSB first)
y_value[63:0] - the 64-bit product output (32×32 = up to 64 bits)

It takes 32 clock cycles to produce a result,  one cycle per bit of a. That's the trade-off vs a fully parallel multiplier: much less silicon area, but slower.

Step 6 - Run the SPM flow

From inside the nix-shell:

librelane librelane/examples/spm/config.yaml

(Some versions may use config.json instead.)

Step 7 - What the flow does

Your run executes the full ASIC pipeline:

    Verilator linting
    Yosys synthesis
    Floorplanning
    Power grid generation
    Placement
    Clock tree synthesis
    Routing
    Static timing analysis
    DRC checks (Magic and KLayout)
    LVS checks (Netgen)
    Final GDS generation

Your log confirms the flow completed successfully.

Step 8 - Locate the final layout

Use the final GDS file:

runs/RUN_2026-06-08_19-04-52/final/gds/spm.gds

Step 9 - Open the layout

In KLayout:

klayout runs/RUN_2026-06-08_19-04-52/final/gds/spm.gds

If KLayout is not available in your environment:

nix-shell -p klayout

Step 10 - Understanding additional outputs

You may also see other GDS files:

    Magic streamout:

    runs/.../57-magic-streamout/spm.gds

    KLayout streamout:

    runs/.../58-klayout-streamout/spm.klayout.gds

    Final signoff layout (use this one):

    runs/.../final/gds/spm.gds

Only the final directory is the authoritative output.

I reccomend you take a good long look at the log for detailed run infromation:

vim runs/RUN_2026-06-08_19-04-52/flow.log

Summary

You successfully completed a full ASIC digital backend flow using:

    Nix for environment management
    LibreLane for automation
    Sky130 PDK for standard cells
    OpenROAD backend tools

The result is a complete, signoff-clean GDS layout ready for inspection in KLayout.